After completing an integrated circuit (IC) design, an engineer must test the functionality and robustness of his or her design. Unfortunately, there is no easy way to do this without fabricating and packaging a “lot” of ICs, in accordance with the design. As is known in the art, a “lot” of ICs may comprise dozens, hundreds, or even thousands of ICs.
If during test, a design flaw or manufacturing error is identified within one of the packaged ICs, then the entire lot of ICs is typically scrapped, as the permanent nature of an IC's packaging has made the repair of any defect interior to the IC's package difficult at best.
If a defect that is interior to a packaged IC is not identified until the packaged IC has been assembled onto a circuit board, then the defective part must be removed and replaced through the undesirable rework process (commonly referred to in the electronic industry as the “Known Good Die” problem).
In addition to the repair issue, packaged ICs are problematic from a development perspective. Typically, an engineer will experiment with different circuit layouts while designing an IC, in order to optimize the IC's design. If a design is believed to have merit, a “lot” of ICs is fabricated and packaged for testing. Design flaws and poor performing circuitry are then identified; the remainder of the ICs are scrapped; and the “design and test” cycle is repeated. The permanency of an IC's package therefore turns the development of a functional and robust IC into a serial process.
Although the above problems are only representative of the types of problems that can be encountered during an IC's development (and only some of the above problems may be encountered during the development of any particular IC), encountering any of these problems leads to a long and costly product development cycle.